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Macros</h2></td></tr>
<tr class="memitem:ga12b802c8f83b2a1b48d1322a7458ae34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__canfd__v1__0.html#ga12b802c8f83b2a1b48d1322a7458ae34">XCanFd_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:ga12b802c8f83b2a1b48d1322a7458ae34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d131863301cf6d7de97e223530acbe2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__canfd__v1__0.html#ga6d131863301cf6d7de97e223530acbe2">XCanFd_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="separator:ga6d131863301cf6d7de97e223530acbe2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the CAN. Each register is 32 bits.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Mail box mode registers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">TxBuffer Element ID Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Tx Message Buffer Element Start Address - 0x0100 (2304 Bytes) End Address - 0x09FF </p>
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<tr><td colspan="2"><div class="groupHeader">TxBuffer Element DLC Registers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">TxBuffer Element DW Registers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Rx Message Buffer Element ID Registers.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Start Address - 0x1100 (2304 Bytes) End Address - 0x19FF </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Rx Message Buffer Element DLC Registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Rx Message Buffer Element DW Registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Rx Message Buffer Element ID,DLC,DW Sizes.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">EDL and BRS Masks.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Acceptance Filter Mask Registers</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Software Reset Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Mode Select Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Baud Rate Prescaler register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bit Timing Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Fast Bit Timing Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error Counter Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status/Enable/Clear Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit Ready request All Mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Mask/Acceptance Filter ID) </p>
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<tr><td colspan="2"><div class="groupHeader">CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Acceptance Filter Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN Recieve FIFO Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN TxBuffer Ready Request Served Interrupt Enable Register Masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN TxBuffer Cancel Request Served Interrupt Enable Register Masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN RxBuffer Full Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CAN frame length constants</div></td></tr>
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